1. Technical Field
This invention relates in general to multi-processor architectures and, more particularly, to a shared translation lookaside buffer in a multi-processor architecture.
2. Description of the Related Art
Many new electronic devices make use of a multi-processor environment that includes DSPs (digital signal processors), MPUs (microprocessor units), DMA (direct memory access units) processors, and shared memories.
The types of tasks performed by a device often have specific real time constraints due to the signals that they are processing. For example, DSPs are commonly used in devices where video and audio processing and voice recognition are supported. These functions can be significantly degraded if part of the multi-processor system must suspend processing while waiting for an event to occur. Performing memory address translations from virtual address used by a task to physical addresses necessary to access the physical memory can be time consuming and degrade performance for a real-time task. To reduce the latencies caused by address translation, a TLB (translation lookaside buffer) is commonly provided as part of a MMU (memory management unit). The translation lookaside buffer caches recently accessed memory locations. At the beginning of a memory access, the TLB is accessed. When a TLB (translation lookaside buffer) cache does not contain the information corresponding to the current access (i.e., a TLB-xe2x80x9cmissxe2x80x9d or xe2x80x9cpage faultxe2x80x9d), the information must be retrieved from tables (xe2x80x9ctable walkingxe2x80x9d), located in main memory. This operation takes tens to hundreds of microprocessor cycles. While the MMU is walking the tables, the operation of the core is blocked, resulting in degraded or errant performance of the processor.
In a multiprocessor system, several separate processing devices may be performing virtual address translation in order to access the physical memory. In one solution shown in FIG. 1, of the type used by the ARM MEMC2, a multiprocessor device 10 uses a shared TLB 12 accessible by multiple processing devices 14 (individually referenced as processing devices 14a-c). Each processing device 14 has a unique requester identifier that is concatenated to a virtual address to form a modified virtual address. The concatenation is performed in order to present unique virtual addresses to the shared TLB 12, since the virtual address range used by the various processors that access the shared TLB 12 may otherwise overlap, thereby presenting a possibility that the wrong physical address may be retrieved from the TLB 12.
If there is a miss in the shared TLB 12, the virtual address is translated to a physical address through translation tables 16 (individually referenced as translation tables 16a-c in FIG. 1) in the physical memory 18. The requester identifier in the concatenated address provides a starting base address in the external memory""s translation table section. Thus, each potential requester has its own translation table under this approach, which is an inefficient use of memory and provides no flexibility in translating a virtual address.
Accordingly, there is a need for a flexible method and circuit for translating virtual addresses to physical addresses in a multiprocessor device.
In the present invention, an integral multiprocessing device comprises a plurality of processing devices, including one or more master processors, each master processor with one or more associated slave processing devices, and a shared translation lookaside buffer coupled to the plurality of processing devices for storing information relating virtual addresses with physical address in a main memory. The slave processors may access the shared translation lookaside buffer without intervention of the associated master processor.
The present invention provides more efficient operation by allowing certain devices, such as coprocessors and DMA processors, to access a shared TLB to perform logical to physical address translations without interfering with the operation of an associated master processor.